1. Field of the Invention
The present invention relates to display technology, and more specifically, to a low temperature poly-silicon (LTPS) thin-film transistor (TFT) substrate structure and a method of forming the same.
2. Description of the Prior Art
Thin-film transistor liquid crystal display (TFT-LCD) can be achieved by two approaches: polycrystalline silicon (poly-Si) and amorphous silicon (a-Si). Low temperature poly-silicon (LTPS) is the latest generation of TFT-LCD producing technology. The biggest difference between a LTPS TFT-LCD and a conventional a-Si TFT-LCD is that the former responds faster, has higher brightness and resolution, and consumes less power.
The crystalline silicons used by LTPS technology are arrayed more orderly than that used by a-Si technology. Therefore, the electron mobility of LTPS technology is over 100 times higher than that of a-Si technology. The peripheral driver can be built on the same glass substrate, saving space and the cost of driver integrated circuit (IC). Because the driver IC is directly built on the substrate, it reduces the number of external contact points, increases reliability, simplifies maintenance procedure, shortens assembly time, and lowers electromagnetic interference, which shortens the time needed for application system design, and renders more flexibility in design.
FIG. 1 is a diagram of a conventional LTPS TFT substrate. The forming method generally comprises the following steps:
Step 1: Provide a substrate 100 and deposit a buffer layer 200;
Step 2: Deposit an a-Si layer on the buffer layer 200;
Step 3: Anneal the a-Si layer with excimer laser, so that the a-Si layer is turned into a poly-Si layer.
Step 4: Pattern the poly-Si layer through lithography and etching process so to form a first poly-Si region 310 and a second poly-Si region 320. These two regions are arrayed with a space in between.
Step 5: Define a heavily N-doped area and lightly N-doped area on the first poly-Si region 310 and the second poly-Si region 320 respectively. Implant different dosages of P31 in the heavily N-doped area and lightly N-doped area so to form lightly doped drain (LDD) areas.
Step 6: Deposit and pattern a gate insulating layer 500 on the buffer layer 2, the first poly-Si region 310 and the second poly-Si region 320.
Step 7: Deposit and pattern a first metal layer on the gate insulating layer 500 corresponding to the first poly-Si region 310 and the second poly-Si region 320 to form a first gate 610 and a second gate 620.
Step 8: Form an interlayer dielectric (ILD) layer 700 on the gate insulating layer 500. Form via holes 701 leading to the heavily N-doped areas next to the first poly-Si region 310 and the second poly-Si region 320 through the gate insulating layer 500 and the interlayer dielectric layer 700.
Step 9: Deposit and pattern a second metal layer on top of the interlayer dielectric layer 700 to form a first source/drain 810 and a second source/drain 820.
The first source/drain 810 and the second source/drain 820 are in contact with the heavily N-doped areas next to the first poly-Si region 310 and the second poly-Si region 320 through the via holes 701. And then, a complete LTPS TFT substrate is formed through subsequent standard procedure.
A LTPS TFT substrate comprises a display area, and a drive area located in a non-display area. The conventional forming method of the LTPS TFTs results in poorer uniformity in the display area, and lower-than-expected electron mobility of the driver in the drive area, further affecting the quality of LTPS TFT substrates.